• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates in particular to a method of producing on the same substrate (100) at least one first transistor and at least one second transistor having different characteristics, the method comprising at least the following steps: - Realization on a substrate (100) of at least a first grid pattern (200) and at least one second grid pattern (300); - Deposition on the first and second grid pattern (200, 300) of at least: a first protective layer (500) and a second protective layer (600) overlying the first protective layer (500) and made of a material different from that of the first protective layer (500) and; - Masking the second grid pattern (300) by a masking layer (700); - Isotropic etching of the second protective layer (600); - Removing the masking layer (700); - Anisotropic etching of the second protective layer (600) selectively to the first protective layer (500).
    公开号:FR3051597A1
    申请号:FR1654554
    申请日:2016-05-20
    公开日:2017-11-24
    发明作者:Laurent Grenouillet；Sebastien Barnola；Marie-Anne Jaud；Jerome Mazurier；Nicolas Posseme
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    TECHNICAL FIELD OF THE INVENTION
    The present invention relates to the realization on the same substrate of transistors having different characteristics, for example gate oxides whose thicknesses are different. It will find advantageous application the realization of such transistors on a FDSOI type substrate.
    STATE OF THE ART
    For some circuits, it is necessary to produce on the same developed substrate, also called slice or wafer in English, transistors having different characteristics, for example different thicknesses of gate oxide.
    The substrates produced generally comprise a support substrate surmounted by an oxide layer and a semiconductor layer whose thickness is fine. They are called FDSOI (fully depleted Silicon on insulator meaning totally deserted silicon-on-insulator) or PDSOI (partially depleted Silicon on insulator meaning silicon-on-insulator partially deserted) mainly depending on the thickness of the semiconductor layer .
    The transistors that are produced on this type of elaborated substrates have a gate stack comprising in particular a gate usually made of doped silicon or metal, a metal layer and an electrically insulating layer of gate oxide between the active layer and the polycrystalline silicon grid.
    On the same developed substrate, it is possible to produce transistors of a first type having a characteristic different from that of a second type of transistor. For example, transistors of a first type having a first gate oxide thickness and transistors of a second type having a second gate oxide thickness greater than the first thickness may be produced on the same substrate. to operate at higher voltages.
    In order to limit the complexity of the process, many steps are common to the realization of the two types of transistors including the realization of the metal layer, the polysilicon gate, the spacers, the sources and drains.
    The object of the present invention is to propose a solution for reproducibly and simply integrating, on the same substrate, transistors having different characteristics, for example gate oxides whose thicknesses are different.
    SUMMARY OF THE INVENTION
    To achieve this objective, according to one embodiment, the present invention provides a method for producing on the same substrate, preferably of the semiconductor-on-insulator type, at least one first transistor and at least one second transistor, the method comprising at least the following steps: - Realization on a semiconductor-on-insulator substrate of at least a first grid pattern and at least one second grid pattern; - Deposition on the first and second grid pattern of at least: • a first protective layer, • a second protective layer surmounting the first protective layer and made of a material different from that of the first protective layer and ; - Masking the second pattern by a masking layer; - Isotropic etching of the second protective layer on the first pattern, retaining the first protective layer on the first pattern, the second pattern being masked by the masking layer during this isotropic etching; - Removal of the masking layer after the isotropic etching step; Before the masking step or after the step of removing the masking layer: anisotropic etching of the second protective layer selectively to the first protective layer, so as to remove at least partly, preferably all, the second protective layer located on a top of the second grid pattern and retaining at least a portion of, preferably all, the thickness of the second protective layer located on flanks of the second grid pattern.
    Thus, the method according to the invention makes it possible to produce on the flanks of the second pattern spacers of greater thickness than on the flanks of the first pattern.
    The present invention thus proposes a solution for reproducibly and simply integrating, on the same substrate, transistors having different characteristics.
    It offers a particularly advantageous advantage for the realization on the same substrate of transistors whose gate stacks have insulating layers, typically gate oxides, whose thicknesses are different. In practice, it has been found that, with the known solutions, the performances of the transistors whose gate oxides are thicker are often degraded as they are used.
    Consequently, with the known solutions, the performances and the lifetime of the devices comprising these transistors can represent a barrier to their industrialization.
    In the development context of the present invention, it has been noted that with the known solutions, in the transistor having a gate stack with the thickest gate oxide, the electric field is the highest at the interface between source / drain and spacers and not at the gate oxide level, as was predictable.
    This strong electric field can cause the breakdown of the spacer as the operation of the transistor.
    By providing a thicker spacer on the sidewalls of the gate of the second transistor which must withstand higher voltages, the invention makes it possible to eliminate this risk of breakdown.
    Furthermore, the invention makes it possible to keep on the sidewalls of the gate of the first transistor a thin spacer thickness. The invention thus makes it possible to preserve the performance of transistors whose gate oxides are the finest.
    In addition, the invention has a limited complexity compared to conventional solutions in which the gate spacers on the flanks of the first and second transistors are of identical thickness. In particular, the method according to the invention does not require an additional mask of lithography. In particular, advantageously, the mask level for introducing the difference in thickness on the spacer is the same as that used to induce the gate oxide difference.
    In addition, this method does not require additional overgrafting which could deteriorate the active layer.
    The method according to the invention is thus compatible with the subsequent steps which are conventional to finalize the realization of the transistors.
    Thus, the invention provides an efficient, easily industrializable and inexpensive solution to improve the performance and life of devices with different characteristics, for example transistors whose gate oxides have different thicknesses.
    It is particularly advantageous for producing FDSOI transistors. The invention nevertheless applies in particular to transistors formed on bulk substrates (in English "bulk") or on substrates of PDSOI type.
    Optionally, the invention may furthermore have at least one of the following optional features: According to one embodiment, the first grid pattern is a first grid stack, and the second grid pattern is a second grid pattern. grid stack.
    According to another embodiment, the first grid pattern is a sacrificial pattern and the second pattern is a sacrificial pattern. The method comprises, after said step of selectively etching the modified portions, a step of replacing the first and second sacrificial patterns with patterns respectively forming a first gate stack and a second gate stack. According to another embodiment, each of the first and second grid stacks comprises at least one insulating layer, typically a gate oxide, the thickness of the insulating layer of the second stack being greater than the thickness of the insulating layer of the first stack.
    According to one embodiment, the thickness of the gate oxide of the first stack is between 0 and 3 nm (10'® meters) and preferably between 0 and 1.5 nm.
    According to one embodiment, the thickness of the gate oxide of the second stack is between 1.5 and 8 nm, preferably between 2 and 6 nm and preferably between 2 and 3.5 nm.
    According to one embodiment, the grid pattern is intended to form a gate for the transistor. The grid pattern is then functional. It is then a process that can be described as "gâte first", that is to say in which the grid is carried out beforehand. According to another embodiment, the grid pattern is intended to be removed, after forming the spacers, to then be replaced by a functional grid pattern. The grid pattern is then sacrificial. It is then a process that can be described as "gâte last", that is to say in which the grid is made in a second time.
    According to one embodiment, the method comprises, before the deposition step of the first and second protective layer, a deposition step on the first and second patterns of a third protective layer disposed under the first layer of protection and covering the first and second grounds. The third protective layer is made of a material that allows the material of the first protective layer to be etched selectively to the material of the third protective layer. The method comprises, after the anisotropic etching of the second protective layer selectively to the first protective layer: a step of etching the first protective layer selectively to the third protective layer so as to remove the first layer on the first pattern protection and to preserve the third layer of protection.
    According to one embodiment, the third protective layer is made of nitride, preferably of silicon nitride or of a material having a dielectric constant of less than 7. The third protective layer is made of a material identical to that of the second layer of protection.
    According to one embodiment, the method comprises, after the step of anisotropic etching of the second protective layer, a step of removing the first protective layer located on the top of the second pattern, on the first pattern and between the first and second pattern, by selective etching of the material of the first protective layer with respect to the material of the second protective layer and the material of the third protective layer.
    According to one embodiment, the method comprises, after the step of removing the first layer on the first pattern, a step of depositing an encapsulation layer of a material having a dielectric constant less than or equal to 8 on the minus the second reason.
    This step makes it possible to fill an opening in the second protective layer of the second pattern and by which the first protective layer present on the flanks of the second pattern is made accessible during the step of removing the first protective layer on the top the second motif. This step thus makes it possible to encapsulate and thus protect the spacer formed by the first layer on the second pattern. Thus, during an etching or a subsequent cleaning, for example based on HF, the spacer formed by the first protective layer on the sides of the second pattern is not degraded.
    According to one embodiment, the substrate is of semiconductor-on-insulator type. Alternatively, it may be a massive substrate, usually referred to as "bulk".
    According to one embodiment, the second protective layer is made of nitride, preferably silicon nitride (SiN), and the first protective layer is an oxide, preferably silicon oxide (SiO 2).
    According to one embodiment, the isotropic etching step of the second protective layer is wet etching, preferably based on a solution of hot H3PO4.
    According to one embodiment, the isotropic etching step of the second protective layer is a dry etching, preferably using a fluorocarbon or fluorinated chemistry.
    According to one embodiment, the dry etching is carried out in a plasma reactor in which a bias bias voltage and / or the voltage of the source is pulsed. This makes it possible to improve isotropy of the engraving.
    According to one embodiment, the removal of the masking layer is performed by etching the masking layer relative to the first protective layer.
    According to one embodiment, the etching of the masking layer is a dry etching based on a reducing or oxidizing chemistry.
    According to one embodiment, the masking layer is a resin. The removal of the masking layer comprises dry etching, preferably based on a mixture of N 2 / H 2 and then wet cleaning, preferably based on SC 1 (NH 4 OH -H 2 O 2).
    According to one embodiment, the anisotropic etching of the second protective layer selectively to the first protective layer is performed after the step of removing the masking layer.
    Starting with the isotropic etching and then performing the anisotropic etching offers the advantage of allowing the stress to be relaxed on the consumption of layers such as SiO 2 which must not be consumed during the etching of the protective layers.
    Alternatively, the anisotropic etching of the second protective layer selectively to the first protective layer is performed before said masking step.
    According to one embodiment, the second protective layer is a nitride or a material having a dielectric constant less than 7 and said anisotropic etching step of the second protective layer comprises: - a protective step by forming a protective film oxide on the first and second patterns; anisotropic etching of the oxide protective film outside the flanks of the first and second patterns so as to keep the oxide protective film only on the flanks of the first and second patterns; the etching of at least a portion of the second protective layer located on a vertex and on either side of the second pattern, the etching being selective with respect to the protective oxide film situated on the flanks of the first and second patterns and the first layer of protection located on the top of the first pattern.
    The formation of the protective oxide film makes it possible to effectively protect the second protective layer present on the flanks of the second pattern during the etching of the second layer on the top of the second pattern.
    Moreover, this step makes it possible to keep at least a portion of the first protective layer on the first pattern.
    Furthermore, optionally, the invention may furthermore have at least one of the following optional features:
    According to one embodiment, the method comprises a step of supergrading to completely remove the second protective layer on the top of the second pattern, said supergraft being selective of the second protective layer vis-à-vis the first protective layer.
    According to one embodiment, said overgrafting is an anisotropic etching having a main direction of etching perpendicular to said substrate.
    According to one embodiment, the second protective layer is made of nitride, preferably of silicon nitride (SiN) or of a material whose dielectric constant is less than 7, the first protective layer is an oxide, preferably an oxide of silicon (SiO2) and the oxide protective film is formed from an oxygen-based plasma.
    According to one embodiment, the method comprises, after the step of anisotropic etching of the second protective layer, a step of removing the first protective layer located on the top of the second pattern, on the first pattern and between the first and second pattern, by selective etching of the material of the first protective layer vis-à-vis the material of the second protective layer.
    According to one embodiment, the method then comprises a step of depositing a third protective layer covering the first and second patterns.
    Another aspect of the present invention relates to a microelectronic device comprising on the same semiconductor-on-insulator substrate at least one first transistor and at least one second transistor each having a grid pattern and spacers located on the sides of the patterns. each grid pattern comprises a gate stack comprising at least one gate and an insulating layer located between the gate and an active layer of said substrate. The insulating gate layer of the second transistor has a thickness greater than that of the pattern of the first transistor. The spacers of the second transistor are thicker than the spacers of the first transistor.
    By microelectronic device is meant any type of device made with microelectronics means. These devices include, in addition to purely electronic devices, micromechanical or electromechanical devices (MEMS, NEMS ...) as well as optical or optoelectronic devices (MOEMS ...).
    Optionally, the substrate is of the FDSOI type.
    Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other benefits may be incorporated.
    BRIEF DESCRIPTION OF THE FIGURES
    The objects, objects, as well as the features and advantages of the invention will become more apparent from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:
    FIGURE 1 is a schematic representation of an elaborate substrate comprising two grid patterns whose gate oxides have different thicknesses.
    FIGS. 2 to 12 illustrate steps of an embodiment of the method according to the invention.
    FIGURE 13 illustrates a step of an alternative embodiment.
    FIG. 14 summarizes certain steps of two examples of method according to the invention.
    The drawings are given by way of examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily at the scale of practical applications. In particular, the relative thicknesses of the different layers and films are not representative of reality.
    DETAILED DESCRIPTION OF THE INVENTION
    It is specified that in the context of the present invention, the term "over", "overcomes", "covers" or "underlying" or their equivalents do not necessarily mean "in contact with". For example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with one another, but that means that the first layer at least partially covers the second layer. being either directly in contact with it or separated from it by at least one other layer or at least one other element.
    With reference to FIGS. 1 to 13, an exemplary method according to the invention will now be described.
    FIG. 1 illustrates a structure from which the steps of the method according to the invention are implemented. This structure includes transistors being formed.
    This structure comprises: an elaborate substrate 100 of semiconductor on insulator (SOI) type. In the illustrated example, this elaborated substrate successively comprises a support layer 101; for example monocrystalline silicon, polycrystalline or amorphous; an insulating layer 102, usually called buried oxide (BOX for Buried Oxide in English) and a semiconductor active layer 103 for forming a conduction channel of a transistor. The latter is for example silicon (Si), germanium (Ge) or silicon-germanium (SiGe), preferably monocrystalline. grid patterns 200, 300. In the illustrated non-limiting example, the grid patterns 200, 300 each form a stack of several layers. These patterns 200, 300 are intended to be retained in the final transistors (gate-first method). According to an alternative embodiment that is not illustrated, the grid patterns 200, 300 are sacrificial patterns which are intended to be removed after the spacers have been made, and then to be replaced by another gate preferably forming a stack (a method of type gust last). ). The invention covers this alternative embodiment. In the remainder of the description, which illustrates an embodiment of the type first step with reference to the figures, the term "stack" or "pattern" will be used as well. Typically, the grid stacks comprise each comprising at least one gate 204, 304 usually made of polycrystalline silicon or metal and an insulating layer usually referred to as gate oxide 201, 301 located under the gate 204, 304 and through which an electric field will be able to develop to create an underlying conduction channel between source and drain when a sufficient voltage is applied to the gate 204, 304.
    Preferably, the gate stack also comprises: a metal layer often described as a metal gate 203, 303 and located between the gate 204, 304 and the gate oxide 201, 301; - A dielectric layer 202, 302, called "high-k", that is to say made of a high permittivity material. This layer is located between the gate oxide 201, 301 and the metal gate 203, 303. - A hard mask 205, 305 of protection which will be removed later to allow the resumption of contact on the gate 204, 304. This hard mask 205, 305, which remains in place after etching the gate 204, 304, is typically made of SiO 2 or silicon nitride (SiN). Its role is to protect the top of the gate 204, 304 from any damage during the completion of the following steps and in particular those of etching spacers. A thin oxide layer can be found between the polycrystalline silicon of the gate and the hard nitride mask.
    Preferably, the gate oxide insulating layer 201, 301 is disposed in contact with the active layer 103 forming the conduction channel and in contact with the high-permittivity layer 202, 302. Preferably, the metal layer 203, 303 is disposed in contact with the high-permittivity layer 202, 302 and in contact with the gate 204, 304.
    According to another embodiment, the metal layer 203, 303 and / or the high-permittivity layer 202, 302 are absent.
    According to another embodiment, the hard mask 205, 305 and a protective layer 400 detailed below are both formed of silicon nitride (SiN).
    The same elaborate substrate 100 supports a plurality of transistors and therefore gate stacks. For some applications, it is necessary to have transistors whose properties are different. Thus, some transistors must have a gate oxide 301 whose thickness is greater than that of the gate oxide 201 of other transistors.
    FIG. 1 thus represents a grid stack 300 whose thickness of the gate oxide 301 is greater than that of the oxide of the gate 201 of the stack 200. By way of non-limiting example, it is possible to have on the same developed substrate 100: - Transistors whose gate oxide has a thickness between 0 and 1.5 nm. These transistors are known to operate at a voltage Vdd of between 0.8V and 1V. These transistors are sometimes called SG or G01. The thickness of the spacers is measured perpendicularly to the plane containing the flanks 210, 310 of the grids 204, 304, i.e. in this example, in a direction parallel to the main plane in which the substrate 100 extends. This thickness is measured horizontally in the figures. transistors whose gate oxide has a thickness of between 2 and 5 nm, and more often between 2 and 3.5 nm. These transistors are known to operate at a voltage Vdd of between 1.5V and 3.5V. Thus the breakdown voltage for these transistors is higher than the maximum voltage applied to the gate oxide. These transistors are sometimes called EG or G02. transistors whose gate oxide has a thickness of between 3 and 6 nm are known to operate at a voltage Vdd greater than 3V. Thus the breakdown voltage for these transistors is higher than the maximum voltage applied to the gate oxide. These transistors are sometimes called ZG or G03. - The structure illustrated in Figure 1 also shows the presence of isolation trench 800 through the entire active layer 103 to isolate two adjacent transistors. These isolation trenches 800 extend through the entire thickness of the active layer 103 and into the support layer 101. These isolation trenches are typically made of oxide, typically SiO 2. - The structure illustrated in Figure 1 also shows the presence of protective layers for forming spacers on the sides 210, 310 of the grids 204, 304.
    These protective layers 400, 500, 600 are three in this embodiment. Nevertheless, we could only have two or have four or more.
    To maintain high performance, especially at transistors whose gate oxides are fine, it is necessary to have fine spacers.
    Typically, for transistors whose gate oxides 201 have a thickness of the order of 0 to 1.5 nm, the total thickness of the layers forming a spacer on the flanks of the grid stacks 200 should preferably have a lower thickness. at 9 nm.
    Moreover, in order to limit the complexity of the processes and to limit their cost, it is preferable that the spacers of transistors of two different types are made during the same steps.
    This leads to the fact that, in known processes, the spacers of the transistors having thicker gate oxides are also less than 9 nm.
    In the context of the development of the present invention, it has been identified that this thickness often leads to a breakdown at the spacers of the thick gate oxide transistors, thereby deteriorating the reliability and the lifetime of the devices incorporating this type. of transistors.
    The following steps make it possible to remedy this problem by forming thicker spacers on the sidewalls 310 of the stacks 300 whose gate oxide 301 is thicker, while limiting the complexity of the process.
    The protective layers illustrated in FIG. 1 comprise: a protective layer 400, usually referred to as "spacer 0". This layer has a thickness of between 3 and 10 nm without this being limiting and preferably of the order of 4 to 8 nm. It is for example made of silicon nitride (SiN) or of a material with a low dielectric constant (k less than 7). It may for example be in a porous material.
    In the context of the present invention, the term porous layer, a layer whose presence of vacuum in the film is greater than 5% and preferably between 5 and 10%. - A protective layer 500, usually called "spacer 1". This layer has a thickness of between 2 and 6 nm without this being limiting and preferably of the order of 3 nm. It is for example made of silicon oxide (SiO 2). This layer is preferably obtained by deposition. Advantageously, to densify the oxide, a thermal annealing step is carried out, for example of the anneal spike type. Such a step makes it possible to rise high in temperature over a very short duration (maximum one second). The densification of the oxide can also be done naturally during the deposition of the layer 600, which is typically at a temperature of the order of 630 ° C for a period greater than 10 minutes. - A protective layer 600, usually referred to as "spacer 2". This layer has a thickness of between 2 and 16 nm without this being limiting and preferably of the order of 10 nm. It is for example silicon nitride (SiN). or in a material with a low dielectric constant (k less than 7). It may for example be in a porous material.
    The layers 400 and 600, when in a low-k material, ie with a low permittivity, generally comprise at least one of the following species or a combination of these species: silicon (Si), carbon (C), boron (B), nitrogen (N), hydrogen (H). They are for example formed in one of the following materials: SiCO, SiC, SiCN, SiOCN or SiCBN. These layers are porous or not.
    The dielectric constant of these layers is measured for example by the conventional method known as the mercury drop.
    The layers 400, 500, 600 are all obtained by a conformal deposition, that is to say that they have a constant thickness over the entire plate and in particular on the sides 210, 310 and the vertices 220, 320 of the stacks 200, 300 grid as well as outside grid stacks 200, 300.
    FIG. 2 illustrates a following step during which a masking layer 700 is formed to entirely cover the second grid stack 300, that is to say one having a gate oxide thickness 301 greater than that of the first 200 This masking layer 700 is typically a resin layer, deposited full plate, and then open at the first stack 200 by one of the conventional lithography techniques.
    In the context of the present invention, the resin is an organic or organo-mineral material that can be shaped by exposure to an electron beam, photons or X-rays or mechanically. The next step, the result of which is illustrated in FIG. 3, aims at removing the second protective layer 600 which covers the first grid stack 200. For this, etching of this layer 600 without etching the first protective layer 500. Furthermore the second protective layer 600, protected by the masking layer 700, remains in place.
    For example, if the first protective layer 500 is made of SiO 2 and the second protective layer 600 is made of silicon nitride, this latter layer will be removed selectively from the first protective layer 500 by wet etching, for example with a solution based on of H3P04. It is also possible and preferentially to remove the second protective layer 600 by dry etching carried out for example in an inductively coupled reactor (ICP), capacitive (CCP) or microwave. If this layer 600 is made of SiN or a material with a dielectric constant of less than 7, a fluorine-based chemistry such as fluorinated or fluorocarbon chemistry will be used for example. This type of etching makes it possible to be very selective with respect to the SiO 2 which is a good candidate for the first protective layer 500. Preferably, the parameters will be adjusted in order to obtain an isotropic etching. The bias voltage (bias) will be lowered in the case of an inductively coupled or capacitive plasma. It will also be possible to draw the bias voltage and / or the voltage of the source to improve the isotropy of the etching. By way of example, the fluorinated chemistry may be based on CxFyHz, SF6 or NF3 diluted or not with other gases such as HBr, N2, Ar, He, H2, CxHyHz. For example, an etching carried out in an inductively coupled reactor will be chosen, for a pressure of 90 mTorr, 600 W of source power, 50 sccm of SF 6, 50 sc cm of HBr, substrate temperature of 60 ° C., the time will be adjusted according to the thickness of nitride to be etched.
    As illustrated in FIG. 4, the masking layer 700 is then removed. Naturally, this shrinkage is selective of the material of the first layer 500 in order to preserve the latter on the first stack 200. When this masking layer 700 is a photosensitive resin, it is for example removed in a capacitively coupled or coupled reactor. inductive or microwave using oxidative or reducing chemistry. For example, a gaseous mixture of N 2 and H 2 can be injected into a plasma reactor for etching and then wet cleaned to remove resin residues. This cleaning can be performed using an SC1 solution. At this stage, the initial thickness of the first layer 500 is retained in its entirety or is at most very little consumed.
    FIGS. 5 to 7 are intended to anisotropically etch the second layer 600 in order to eliminate or reduce the thickness of this layer 600 on the top 320 of the second stack 300 while maintaining a high thickness of this layer 600 on its sidewalls 310 and without significantly altering the first protective layer 500.
    Figure 5 illustrates an advantageous but only optional step. It aims to protect the second protective layer 600 at the sidewalls 310 of the second stack 300. For this, an oxide protective film 900 is formed on the surface of this layer 500. For example, 02 is injected into a reactor ICP or CCP plasma with the following parameters: - Pressure: 10 milli Torr - Power of the source: 1000 Watts - Flow rate of 02: 200 sccm (cubic centimeters per minute under standard conditions of pressure and temperature). Typically a flow rate is measured with a flow meter associated with the reactor.
    - Substrate temperature 60 ° C - Duration: 30 seconds
    These conditions cause the formation of an oxide film 900 of about 1 to 2 nm on the surface of the plate, that is to say on the surface of the second protective layer 600 as well as on the surface of the first protective layer 500.
    FIG. 6 illustrates an anisotropic etching step carried out in a preferred direction which is perpendicular to the main plane in which the substrate 100 extends. Thus, during this anisotropic etching, the protective film 900 is removed on the surfaces parallel to the main plane in which the substrate 100 extends. This protective film 900 is removed on the vertices 220, 320 of the stacks 200, 300 and between the stacks 200, 300.
    This anisotropic etching also removes a portion of the thickness of the second protective layer 600 located on the top 320 of the second stack 300.
    This engraving engraves the second protective layer 600 much faster than the first protective layer 500, so that after this anisotropic etching, the thickness of the first protective layer 500 is not consumed at all. or is only partially engraved on the top 220 of the first stack 200.
    For example, the anisotropic etching removes all the protective film 900 on the top 220, 320 of the stacks 200, 300 and between them and consumes about 3 nm of the second protective layer 600 on the top 320 of the second stack 300. then a thickness of 1 nm of the second layer 600 on the top 320.
    FIG. 7 illustrates a supergrafting step for removing the thickness of the second protective layer 600 that remains on the top 320 of the second stack 300. This residual thickness is about 1 nm in this non-limiting example. This etching is selective material of this layer 600 vis-à-vis that of the first layer 500 which is not or that little consumed. As it appears in FIG. 7, the second layer 600 is then removed everywhere except for the sidewalls 310 of the second stack 300. The residual portions 610 of the second protective layer 600 then form spacers 610. This etching is preferably anisotropic. .
    FIG. 8 illustrates the removal of the first protective layer 500. This withdrawal reveals the third protective layer 400, intended to form the spacers for the first stack 200, that is to say the stack having a low thickness. gate oxide 201.
    In the case where the first protective layer 500 is an oxide such as SiO 2, this shrinkage is advantageously carried out by wet etching, for example with a dilute solution of HF.
    This engraving engraves the first layer 500 selectively at the spacers 610 of the second layer 600 and the third layer 400, so that the latter is only a little and preferably is not engraved at all.
    It follows from this step that slight cavities 306 can appear between the spacers 610 and the third layer 400 where the first layer 500 is accessible.
    As illustrated in FIG. 9, in order to protect the first protective layer 500, it is possible to encapsulate the latter by forming an encapsulation layer 1000 which fills these cavities 306.
    This encapsulation layer 1000 is for example a nitride layer (SiN for example) or a low-k layer, that is to say with a dielectric constant of less than 7.
    In this case, the thickness of the third protective layer 400 must be chosen to obtain, after deposition of the encapsulation layer 1000, the desired thickness to protect the flanks 210 of the first stack 200.
    As illustrated in FIG. 9, the first stack 200 has on its flanks 210 spacers 250 constituted by the following layers: - Third protective layer 400 and optionally the encapsulation layer 1000;
    The second stack 300 has on its flanks 310 spacers 250 constituted by the following layers: - Third protective layer 400, first protective layer 500, spacers 610 formed by the second protective layer 600 and optionally the encapsulation layer 1000. Thus the flanks 310 of the gate stack 300 having a thicker gate oxide 301 are protected by a spacer thickness much greater than the flanks 210 of the stack 200 in which the gate oxide 201 is thin.
    Note that the structure obtained has the advantage that the active layer 103 is, outside the grid stacks 200, 300, surmounted by a layer 400 of constant thickness on the plate. Therefore, the same anisotropic etching of the third protective layer 400 makes it possible to remove the latter from both sides of the stacks 200, 300 in order to expose the active layer 103 for the formation of the source and drain, typically by epitaxy from the active layer 103. The fact that before etching this third layer 400 has a constant thickness allows good control of its etching to remove it entirely but without altering the active layer 103 underlying.
    For example, to remove the third protective layer 400 between the stacks 200, 300, one can proceed to the following steps, if the layer 400 is silicon nitride (SiN) or low-k material. - Deposition of a protective film 1100 as shown in Figure 10. In this figure, for reasons of clarity, the optional encapsulation layer 1000 is not shown. Naturally, if this encapsulation layer 1000 is formed as illustrated in FIG. 9, it will be present under the protective film 1100. This protective film 1100 is for example obtained by plasma deposition of an oxide film on the entire plate. Preferably, this protective film 1100 is produced in the same reactor as the subsequent anisotropic etching of the third protective layer 400. It covers the flanks 210, 310, the vertices 220, 320 of the grid stacks 200, 300 and the regions between the stacks 200, 300.
    For example, the following conditions are applied in a plasma ICP reactor: - Pressure: 10 milli Torr - Power of the source: 1000 Watts - Flow rate of 02: 200 sccm
    Substrate Temperature 60 ° C. Removal of the protective film 1100 in the bottom of the structure and consequently on the vertices 220, 320 of the stacks 200, 300 while keeping it on the sidewalls 210, 310. This step is illustrated in FIG. figure 11.
    This shrinkage preferably comprises anisotropic etching in a preferred direction parallel to the flanks 210, 310. This etching is for example carried out using a fluorinated or fluorocarbon plasma. The conditions may for example be as follows:
    Main Engraving: • Pressure: 5 milli Torr • Source Power: 300 Watts • Bias Voltage: 65 Volts • Flow rate of CHF3: 30 sccm • Flow of He: 220 sccm
    Temperature 110 ° C
    With these conditions, the etching rate of the third protective layer 400 of silicon nitride is of the order of 30 nm / min.
    It is then possible to carry out a step of selective over-etching with Si and SiO 2, for example with the following conditions: • Pressure: 90 milli Torr • Power of the source: 400 Watts • Bias bias voltage Vb: 250 volts • Flow rate CHF3: 200 sccm • Flow rate of O2: 200 sccm • Flow rate of He: 120 sccm • Flow rate of CH4: 20 sccm
    • Substrate temperature 60 ° C • Polarization pulse (bias) 50% • Frequency 500Hz - Removal of material from the third protective layer 400 selectively to the protective film 1100 oxide. This etching must be highly selective vis-à-vis the protective film 1100 so that the latter effectively protects the already formed spacers. This etching is also highly selective vis-à-vis the material of the active layer 103 for forming the channel so as not to consume or degrade the latter.
    The etching does not have an infinite selectivity with respect to the protective film 1100, the latter is nevertheless consumed during the etching. This film 1100, however, allows better dimensional control by delaying the effect of lateral attack, even for anisotropic etching. At this stage of the process, only thicknesses of the first protective layer 500, the second protective layer 600 and the third protective layer 400 remain on the sidewalls 310 of the second stack 300. On the sidewalls 210 of the second first stack 200 only the third layer 400 remains.
    According to another embodiment, the steps described with reference to FIGS. 9 and 10 are replaced by an anisotropic etching step of the third protection layer 400 in the preferred direction 10. This etching is a dry etching. The result of this etching is illustrated in FIG. 13. The third protective layer 400 is withdrawn on the tops and between the stacks 200, 300. On the other hand, it remains on the flanks 210 of the first stack 200 (as well as on the flanks 310 of the second stack 300 since these are covered by the other spacers formed by the first 500 and second 600 layers). The steps mentioned below can be performed from the result of the step illustrated in FIG. 13. This embodiment has the particular advantage of reducing the number of steps and thus of being less expensive. At this stage of the process, the total thicknesses of the spacers are, for example, the following: first stack 200 with gate oxide 201 end: e250 = 6 nm - second stack 300 with 301 thick gate oxide e350 = 20 nm. As illustrated in FIG. 11, these thicknesses are taken perpendicularly to the main plane in which the flanks 210, 310 of the grid stacks 200, 300 extend.
    Thus, the total spacer thickness for thick gate oxide transistors is about three times higher than for fine gate oxide transistors. This avoids the risk of breakdown.
    Advantageously but only optionally, doping is carried out by inclined implantation (tilted doping) of the sides of the stack 300 having a thicker gate oxide in order to dopate the region of the layer 103 situated under the spacer. This doping makes it possible to preserve or improve the performances of this transistor. This doping comprises, for example, the implantation of Arsenic (As), Phosphorus (P) species for an N-type transistor, or Bore (B), boron difluoride (BF2), or Indium for a P-type transistor in the region. the channel under the thicker spacer
    The spacers are formed on either side of the stacks 200, 300. It is then possible to implement conventional steps to finalize the production of the transistors.
    Among these conventional steps, it is possible, for example, to provide for the growth of the source and drain 1200 by epitaxy from the active layer 103 as illustrated in FIG. 12. Depending on the applications, protection of the P-type transistors (or N) by depositing a resin. This step is preferably carried out before the formation of the oxide protective film 1100 illustrated in FIG.
    In view of the above description, it is clear that the method according to the invention makes it possible to improve the lifetime of the devices integrating on the same chip transistors whose gate thicknesses are different, without increasing significantly the complexity of the manufacturing process. The invention is not limited to the previously described embodiments and extends to all the embodiments covered by the claims.
    For example we can reverse the order of some steps. For example, the step of anisotropic etching of the second protective layer 600 may be performed before masking the second stack 300. In this case, the second protective layer 600 is removed, entirely or partially, on the vertices 220, 320 of the two Stacking 200, 300. However, this layer is preserved on the sides 210, 310 of the two stacks 200, 300. After this anisotropic etching, the masking step of the second stack 300 is carried out in order to allow the isotropic etching of the second layer. 600 covering the first stack 200, in particular at its flanks 210.
    This alternative embodiment is illustrated in FIG. 14 by the dashed arrows.
    The details, examples and advantages of the steps of the embodiment described in detail with reference to FIGS. 1 to 12 apply to this alternative embodiment in which the step of anisotropic etching of the second protective layer 600 is performed before masking. the second stack 300.
    Compared to the embodiment illustrated in the figures, this alternative embodiment has the following advantages:
    Although the invention is particularly advantageous for producing on the same substrate transistors whose gate stacks have insulating layers (typically a gate oxide layer) of different thicknesses, this is not limiting. Indeed the invention also applies to the realization on the same substrate of transistors whose gate stacks have insulating layers of identical thicknesses.
    Moreover, in the illustrated embodiments, the gate stack is made prior to the steps of the invention. These figures thus illustrate a method of type gâte first.
    According to another embodiment covered by the invention, the functional grid stack is produced after the steps of the invention. The grid stack on which the first protective layer is deposited thus forms a sacrificial pattern which will be removed once the spacers have been made. This alternative embodiment is thus a last type of process.
    REFERENCES 100 Prepared substrate 101 Carrier layer 102 Insulating layer 103 Active layer 200 First stack / Pattern 201 Insulating layer of the first stack 202 High-permittivity layer of the first stack 203 Metal grid of the first stack 204 Grid of the first stack 205 Hard mask of the first stack 210 Flank of the first stack 220 Top of the first stack 250 Spacer of the first stack 300 Second stack / Pattern 301 Insulating layer of the second stack 302 High-permittivity layer of the second stack 303 Metal grid of the second stack 304 Grid of the second stack 305 Hard mask of the second stack 306 Cavity 310 Sidewall of the second stack 320 Top of the second stack 350 Spacer of the second stack 400 Third layer of protection 500 First layer of protection 600 Second layer of protection 610 Portion of second layer of protection 700 Masking layer 800 Trench of i solation 900 Protective film 1000 Encapsulation layer 1100 Protective film 1200 Source / Drain
    权利要求:
    Claims (17)
    [1" id="c-fr-0001]
    1. A method of producing on the same substrate (100) at least one first transistor and at least one second transistor, the method comprising at least the following steps: - Realization on a substrate (100) of at least one first grid pattern (200) and at least one second grid pattern (300); - Deposition on the first and second grid pattern (200, 300) of at least: • a first protective layer (500), • a second protective layer (600) overlying the first protective layer (500) and made of a material different from that of the first protective layer (500) and; - Masking the second grid pattern by a masking layer (700); - Isotropic etching of the second protective layer (600) located on the first grid pattern (200), keeping the first protective layer (500) on the first grid pattern (200), the second pattern (300) of grid being masked by the masking layer (700) during this isotropic etching; - Removing the masking layer (700) after the isotropic etching step; - Before the masking step or after the step of removing the masking layer (700): anisotropic etching of the second protective layer (600) selectively to the first protective layer (500), so as to remove the least partly the second protective layer (600) on a top (320) of the second grid pattern (300) and retaining at least a portion of the thickness of the second protective layer (600) on flanks (310) of the second grid pattern (300).
    [2" id="c-fr-0002]
    2. Method according to the preceding claim wherein the first grid pattern (200) is a first grid stack and wherein the second grid pattern (300) is a second grid stack, each of the first and second grid stacks comprises at least one insulating layer (201, 301), typically a gate oxide.
    [3" id="c-fr-0003]
    The method of claim 1 wherein the first grid pattern (200) is a sacrificial pattern, wherein the second pattern (300) is a sacrificial pattern, the method comprising, after said anisotropic etching step of the second layer of protection (600) selectively to the first protection layer (500), a step of replacing the first and second patterns (200, 300) sacrificial by patterns respectively forming a first gate stack and a second gate stack, each of the first and the second gate stack comprises at least one insulating layer (201, 301), typically a gate oxide.
    [4" id="c-fr-0004]
    4. Method according to any one of the two preceding claims wherein the thickness of the insulating layer (301) of the second stack is greater than the thickness of the insulating layer (201) of the first stack.
    [5" id="c-fr-0005]
    5. Method according to the preceding claim wherein the thickness of said insulating layer (201) of the first stack is between 0 and 3 nm (10'® meters) and preferably between 0 and 1.5 nm.
    [6" id="c-fr-0006]
    6. A method according to any one of the preceding claims wherein the thickness of said insulating layer (301) of the second stack is between 1.5 and 8 nm, preferably between 2 and 6 nm and preferably between 2 and 6 nm. 3.5 nm.
    [7" id="c-fr-0007]
    7. Method according to any one of the preceding claims, comprising, before the step of depositing the first and second protective layer (500, 600), a deposition step on the first and second patterns (200, 300). of a third protective layer (400) disposed under the first protective layer (500) and covering the first and second grid patterns (200, 300), the third protective layer (400) being made of a material allowing etching the material of the first protective layer (500) selectively to the material of the third protective layer (400) and wherein the method comprises, after the anisotropic etching of the second protective layer (600) selectively to the first layer protection device (500): a step of etching the first protective layer (500) selectively at the third protective layer (400) so as to remove the first grid pattern (200) from the first protective layer (500) and to keep the third layer of protection (400).
    [8" id="c-fr-0008]
    8. A method according to any one of the preceding claims comprising, after the step of anisotropic etching of the second protective layer (600), a step of removing the first protective layer (500) located on the top (320) of the second grid pattern (300), on the first grid pattern (200) and between the first and second grid patterns (200, 300), by selectively etching the material of the first protective layer (500) vis-à-vis the -vis the material of the second protective layer (600) and the material of the third protective layer (400).
    [9" id="c-fr-0009]
    9. Method according to the preceding claim comprising, after the step of removing the first layer (500) on the first grid pattern (200), a step of depositing an encapsulation layer (1000) of a material having a dielectric constant less than or equal to 8 on at least the second grid pattern (300).
    [10" id="c-fr-0010]
    The method according to any one of the preceding claims, wherein the second protective layer (600) is made of nitride, preferably silicon nitride (SiN), and the first protective layer (500) is an oxide, preferably silicon oxide (SiO2).
    [11" id="c-fr-0011]
    11. A method according to any one of the preceding claims wherein the isotropic etching step of the second protective layer (600) is a wet etching, preferably based on a solution of H3PO4.
    [12" id="c-fr-0012]
    12. A method according to any one of claims 1 to 10 wherein the isotropic etching step of the second protective layer (600) is a dry etching, preferably using a fluorocarbon or fluorinated chemistry and wherein the dry etching is preferably carried out in a plasma reactor in which a bias voltage or the voltage of the source is pulsed.
    [13" id="c-fr-0013]
    A method according to any one of the preceding claims wherein the anisotropic etching of the second protective layer (600) selectively to the first protective layer (500) is performed after the step of removing the masking layer (700). ).
    [14" id="c-fr-0014]
    The method of any one of claims 1 to 12 wherein the anisotropic etching of the second protective layer (600) selectively to the first protective layer (500) is performed prior to said masking step.
    [15" id="c-fr-0015]
    A method according to any preceding claim wherein the second protective layer (600) is a nitride or a material having a dielectric constant less than 7 and said anisotropic etching step of the second protective layer (600) comprises a protective step by forming a protective film (900) of oxide on the first and second grid patterns (200, 300); anisotropic etching of the protective film (900) of oxide outside the flanks (210, 310) of the first and second grid patterns (200, 300) so as to keep the protective film (900) of oxide only on the flanks (210, 310) of the first and second grid patterns (200, 300); etching at least a portion of the second protective layer (600) located on an apex (320) and on either side of the second grid pattern (300), the etching being selective with respect to oxide protective film (900) on the sidewalls (210,310) of the first and second grid patterns (200,300) and the first protective layer (500) on the top (220) of the first pattern (200) grid.
    [16" id="c-fr-0016]
    16. A method according to any one of the preceding claims wherein the second protective layer (600) is nitride, preferably silicon nitride (SiN) or a material whose dielectric constant is less than 7, the first layer protection device (500) is an oxide, preferably a silicon oxide (SiO 2) and the oxide protective film (900) is formed from an oxygen-based plasma.
    [17" id="c-fr-0017]
    17. A microelectronic device comprising on the same semiconductor-on-insulator substrate (100) at least one first transistor and at least one second transistor each having a grid pattern (200, 300) and spacers (250, 350) located flanks (210,310) of gate patterns (200,300), each gate pattern (200,300) comprising a gate stack comprising at least one gate (204,304) and an insulating layer (201,301). ) between the gate (204, 304) and an active layer (103) of said substrate (100), wherein the insulating layer (301) of the gate pattern (300) of the second transistor has a thickness greater than that of the pattern ( 200) of the first transistor, characterized in that the spacers (350) of the second transistor are thicker than the spacers (250) of the first transistor.
    类似技术:
    公开号 | 公开日 | 专利标题
    EP2876677B1|2019-09-18|Method for forming spacers of a transistor gate
    EP2750170A1|2014-07-02|Method for forming spacers of a transistor gate
    FR3023973A1|2016-01-22|METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR
    EP3144973B1|2020-03-04|Method for forming spacers of a transistor gate
    EP3246948B1|2020-11-18|Method for forming, on a single substrate, transistors having different characteristics
    EP2999001B1|2019-09-04|Production of spacers at the edges of a transistor gate
    EP3249689B1|2021-03-17|Method for forming pdsoi and fdsoi transistors on a single substrate
    EP3246953B1|2019-03-20|Method for forming, on a single substrate, transistors having different characteristics
    EP2779223B1|2016-11-23|Method for producing a substrate provided with edge protection
    EP3261124B1|2020-08-19|Method for forming spacers of a transistor gate
    EP3107118B1|2020-02-12|Method for forming spaces of a transistor gate
    EP3506336B1|2020-11-04|Method for etching a three-dimensional dielectric layer
    EP3396704B1|2022-03-09|Method for etching a layer made of sin
    WO2014037411A1|2014-03-13|Process for producing fet transistors
    FR3080486A1|2019-10-25|METHOD FOR FORMING A MICROELECTRONIC DEVICE
    EP3671815A1|2020-06-24|Method for etching a three-dimensional dielectric layer
    FR3047352A1|2017-08-04|METHOD FOR MANUFACTURING A DOPANT TRANSISTOR LOCATED AT THE GRIT APLOMB
    EP3503203A1|2019-06-26|Production of transistors with stressed channels
    EP3107124B1|2018-04-04|Method for forming spacers of a transistor gate
    EP3764390A1|2021-01-13|Method of forming spacers of a transistor
    FR3098978A1|2021-01-22|manufacturing process of transistors
    FR3098981A1|2021-01-22|manufacturing process of transistors
    FR3023408A1|2016-01-08|METHOD FOR MANUFACTURING A DOUBLE GRID MEMORY CELL
    同族专利:
    公开号 | 公开日
    FR3051597B1|2019-11-08|
    US20170358502A1|2017-12-14|
    EP3246948A1|2017-11-22|
    US10347545B2|2019-07-09|
    EP3246948B1|2020-11-18|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20060205134A1|2005-03-10|2006-09-14|Oki Electric Industry Co., Ltd.|Method for manufacturing a semiconductor device and method for regulating speed of forming an insulating film|
    WO2012046365A1|2010-10-08|2012-04-12|パナソニック株式会社|Semiconductor device and method for manufacturing same|
    WO2014162164A1|2013-04-03|2014-10-09|Commissariat A L'energie Atomique Et Aux Eneriges Alternatives|Cmos in situ doped flow with independently tunable spacer thickness|
    US20150035072A1|2013-08-05|2015-02-05|Qualcomm Incorporated|Methods and apparatuses for forming multiple radio frequency components associated with different rf bands on a chip|
    CN102299154B|2010-06-22|2013-06-12|中国科学院微电子研究所|Semiconductor structure and manufacturing method thereof|
    US8450169B2|2010-11-29|2013-05-28|International Business Machines Corporation|Replacement metal gate structures providing independent control on work function and gate leakage current|
    US20160003584A1|2013-07-09|2016-01-07|Eric Durynski|Portable bullet trap|KR20190142881A|2018-06-19|2019-12-30|삼성전자주식회사|Integrated circuit device|
    FR3090997A1|2018-12-20|2020-06-26|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Method for producing a raised source and drain transistor|
    FR3091002B1|2018-12-20|2021-01-08|Commissariat Energie Atomique|Method of etching a three-dimensional dielectric layer|
    法律状态:
    2017-05-31| PLFP| Fee payment|Year of fee payment: 2 |
    2017-11-24| PLSC| Search report ready|Effective date: 20171124 |
    2018-05-28| PLFP| Fee payment|Year of fee payment: 3 |
    2019-05-31| PLFP| Fee payment|Year of fee payment: 4 |
    2020-05-30| PLFP| Fee payment|Year of fee payment: 5 |
    2021-05-31| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1654554|2016-05-20|
    FR1654554A|FR3051597B1|2016-05-20|2016-05-20|METHOD FOR PRODUCING ON THE SAME SUBSTRATE TRANSISTORS HAVING DIFFERENT CHARACTERISTICS|FR1654554A| FR3051597B1|2016-05-20|2016-05-20|METHOD FOR PRODUCING ON THE SAME SUBSTRATE TRANSISTORS HAVING DIFFERENT CHARACTERISTICS|
    EP17171978.4A| EP3246948B1|2016-05-20|2017-05-19|Method for forming, on a single substrate, transistors having different characteristics|
    US15/599,944| US10347545B2|2016-05-20|2017-05-19|Method for producing on the same transistors substrate having different characteristics|
    [返回顶部]